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Renesas unveils Linux-driven RISC-V SoC based on an Andes AX45MP core | #linux | #linuxsecurity | #hacking | #aihp







Renesas announced a headless, 1GHz “RZ/Five” IoT SoC that runs Linux on Andes’ AX45MP RISC-V core with support for up to 4GB DDR4-1600, 1x or 2x GbE ports, 2x CAN, and 2x USB. A SMARC module is in the works.

Renesas has begun sampling the first commercial system-on-chip based on Andes Technology’s 64-bit RISC-V cores. The headless, single-core RZ/Five runs Linux on Andes’ up to 1GHz AndesCore AX45MP core, which was updated for greater performance last December. The SoC is aimed at entry-class social infrastructure gateway control and industrial gateway control.



RZ/Five in 11 x 11mm and 13 x 13mm versions

The RZ/Five is available in two SKUs: a 13 x 13mm, 361-pin model with support for dual Gigabit Ethernet ports and an 11 x 11mm, 266-pin SKU with single-GbE support. The larger model is pin-compatible with the similarly sized single-core, Cortex-A55 powered Renesas RZ/G2UL SoC. Renesas plans to offer a SMARC module based on the RZ/Five that is compatible with its RZ SMARC Evaluation Board kit, which we briefly covered in our RZ/G2UL report.


RZ/Five feature comparison chart with RZ/G2L parts (left) and earlier version of RZ SMARC Evaluation Board ( RZ/G2L carrier)
(click images to enlarge)

Like the single-core AndesCore A45MP, the AndesCore AX45MP has a superscalar, in-order, 8-stage dual-issue architecture. The version used by Renesas enables two optional features of the core: a 256KB L2 cache controller with ECC and a floating-point extension DSP/SIMD. There are also 2x 32Kb L1 cache.

The fact that Renesas chose the AX45MP, which supports up to quad-core clusters, rather than the single-core A45MP, suggests that multi-core successors to RZ/Five may be in the works. Future models could run at up to 2.4GHz, the current limitation of the AX45MP.

The cores are supported by Andes development tools such as AndeSight IDE and Andes Custom Extension framework. As with the RZ/G Series, Renesas is supporting the RZ/Five with a Verified Linux Package (VLP) equipped with Civil Infrastructure Platform (CIP) Linux, an industrial-grade Linux offering long-term maintenance support for more than 10 years.

The RZ/Five is equipped with a Direct Memory Access Controller (DMAC) and 128 Kb system RAM and supports up to 4GB external DDR4-1600 or DDR3L-1333 with ECC support. There is also an Andes Platform-Level Interrupt Controller (PLIC). Renesas has added its DA9062 power management IC, 5P35023 programmable clock generator, AT25QL128A flash memory, and SLG46538 GreenPAK IC, which implements peripheral functions such as system reset.

I/O support includes the 1x or 2x GbE, as well as 2x USB 2.0, 2x CAN, 7x Serial Communication Interface (SCI) including 5x with FIFO. Other interfaces include 4x rSPI, 2x ADC, I2C, SSI, 9-channel timer pulse unit, a clock pulse generator, SPIM, GPIO, 2x SD/MMC, and watchdog and general timers.

There is a -40 to 85℃ operating range, and Renesas is considering a -40 to 125℃ variant. A security chip is optional.

In other news, Renesas announced a Genesis for R-Car cloud-based evaluation environment for its Linux-driven R-Car automotive platform, such as the octa-core -A57 and -A53 R-Car H3 SoC. Renesas also announced a collaboration with Fixstars, which produces CPU/GPU/FPGA acceleration technology, to establish an Automotive SW Platform Lab for developing deep learning software and operating environments for Genesis for R-Car.

 
Further information

The RZ/Five has begun sampling and will begin mass production in July. More information may be found in Renesas’ announcement and RZ/Five product page.
 


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